While laser “melt” anneal processes for transistors are known, they are not typical in high volume logic device manufacturing. One forecasted application of a pulsed laser anneal process is to melt material and advantageously increase the activation of dopants relative to other forms of anneal where the semiconductor is not melted. Transistor parametrics, such as external resistance (Rext), specific contact resistance (Rc), etc. may be improved through such melt anneals. However, one challenge is retaining the high activation levels achieved by the melt anneal as the transistor is processed through a remainder of the manufacturing process because post-melt thermal processes tend to deactivate super-activated regions.
Other challenges of laser melt anneal include pattern effects, maintaining gate metal integrity and/or gate oxide integrity during the melt process, and retaining morphology post-melt (particularly where the transistor has a non-planar architecture).
Techniques and the resulting structures that overcome some or all of these challenges is therefore advantageous.